TSMC has recently unveiled its ambitious semiconductor roadmap, outlining its vision for the future up to the year 2030. The company showcased its plans at the IEDM conference, revealing a roadmap that extends to the production of 1nm transistors and the potential for a trillion transistors in a single package. This aligns with Intel’s parallel vision of achieving one trillion transistors by 2030 using chiplets and advanced packaging technologies.
TSMC’s roadmap includes the possibility of placing a trillion chips on a package through the use of multiple 3D-stacked chiplets. Intel, too, envisions achieving this milestone through chiplets and advanced packaging. TSMC aims to reach 1nm transistors by 2030, allowing for a remarkable 200 billion transistors on a monolithic die. To put this in perspective, Nvidia’s largest monolithic TSMC die, the H100, currently houses 80 billion transistors. Meanwhile, chiplet designs are growing in size, with Intel’s Ponte Vecchio featuring 100 billion transistors and AMD’s MI300 offering 146 billion transistors.
To meet these ambitious goals, TSMC plans to progress through a 2nm process and subsequently move to 1.4nm and 1nm nodes. The roadmap indicates a focus on the 3nm process until 2025, followed by the commencement of 2nm production. By 2028, TSMC aims to implement a 1.4nm A14 process, with the 1nm A10 node scheduled for 2030.
Notably, Intel has its own plans, with the company aiming to produce its 2nm process, known as Intel 20A, in 2024. Following this, Intel plans to advance to 1.8nm (Intel 18A) in 2025. If Intel can meet these targets, it could potentially surpass TSMC for the first time in years, aligning with its “five nodes in four years” plan initiated in 2021. However, as with any technological roadmap, the actual realization of these plans will depend on the successful execution of the outlined milestones.
